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PRELIMINARY
FastEdgeTM Series CY2PP3115
1:15 Differential Fanout Buffer
Features
* Fifteen ECL/PECL differential outputs grouped in four banks * Two ECL/PECLdifferential inputs * Hot-swappable/-insertable * 50-ps output-to-output skew * < 200-ps device-to-device skew * Less than 2-pS intrinsic jitter * < 500-ps propagation delay (typical) * Operation up to 1.5 GHz * PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V * ECL mode supply range: VEE = -2.375V to -3.465V with VCC = 0V * Industrial temperature range: * 52-pin 1.4mm TQFP package * Temperature compensation like 100K ECL -40C to 85C
Description
The CY2PP3115 is a low-skew, low propagation delay 1-to-15 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths which are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2PP3115 may function not only as a differential clock buffer but also as a signal level translator and fanout on ECL/PECL single-ended signal to 15 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-F capacitor. Since the CY2PP3115 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3115 delivers consistent, guaranteed performance over differing platforms.
Block Diagram
FSELA VEE VCC 1 CLK0 CLK0# 0 VCC VEE 1 CLK1 CLK1# VEE CLK_SEL VEE 1 FSELB FSELC QC2 QC3 0 /2 1 /1 0 QB1 QB2 0 QAO QA1
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 14 15 16 17 18 19 20 21 22 23 24 25 26 27
QBO
VCC QA0 QA0# QA1 QA1# VCC QB0 QB0# QB1 QB1# QB2 QB2# VCC
VCC MR FSELA FSELB CLK0
QC0 QC1
1 2 3 4 5 6 7 8 9 10 11 12 13
VCC QC0 QC0# QC1 QC1# QC2 QC2# QC3 QC3# VCC NC NC VCC
CLK0# CLK_SEL CLK1 CLK1# VBB FSELC FSELD VEE
CY2PP3115
VEE MR VEE 0
QD0 QD1 QD2 QD3 QD4
1 FSELD VEE
QD5 VBB
Cypress Semiconductor Corporation Document #: 38-07502 Rev.*A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised November 18, 2003
VCC QD5# QD5 QD4# QD4 QD3# QD3 QD2# QD2 QD1# QD1 QD0# QD0
PRELIMINARY
Pin Description
Pin No. Name[2,3] I/O[1] +PWR I,PD I,PD I,PD I,PC O -PWR I,PD O,OE O,OE O,OE O,OE O,OE O,OE O,OE O,OE Type POWER ECL/PECL ECL/PECL ECL/PECL ECL/PECL Bias POWER ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL ECL/PECL
FastEdgeTM Series CY2PP3115
Description
1,14,27, 30, 39, 40, 47, VCC 52 2 3,4,11,12 5,8 6,9 10 13 28,29 7 26,24,22,20,18,16 25,23,21,19,17,15 38,36,34,32 37,35,33,31 46,44,42 45,43,41 51,49 50,48 MR FSEL(A,B,C,D) CLK(0:1) CLK(0:1)# VBB VEE NC CLK_SEL QD(0:5) QD(0:5)# QC(0:3) QC(0:3)# QB(0:2) QB(0:2)# QA(0:1) QA(0:1)#
Power Supply, positive connection Reset Output Divider Selects Differential Clock Inputs - TRUE Differential Clock Inputs - COMPLIMENT DC Bias Source Power Supply, Negative Connection No Connect. Pad Only Clock Input Select Bank D True Output Bank D Compliment Output Bank C True Output Bank C Compliment Output Bank B True Output Bank B Compliment Output Bank A True Output Bank A Compliment Output
Table 1. Function Table Control Pin FSELA (Asynchronous) FSELB (Asynchronous) FSELC (Asynchronous) FSELD (Asynchronous) CLK_SEL (Asynchronous) MR (Asynchronous) 0 /1 /1 /1 /1 CLK0 Active 1 /2 /2 /2 /2 CLK1 Reset (QX = L and QX# = H)
Governing Agencies
The following agencies provide specifications that apply to the CY2PP3115. The agency name and relevant specification is listed below. Agency Name JEDEC Specification JESD 51 (Theta JA) JESD 8-2 (ECL) JESD 65-A (skew,jitter) 1596.3 (Jitter specs) 94 (Flammability Grading) 883E Method 1012.1 (Thermal Theta JC)
IEEE UL Mil-Spec
Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-down, PU for Pull-up, PC for Pull Center, O for output, OE for open emitter and PWR for Power. 2. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V.
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PRELIMINARY
Absolute Maximum Conditions
.
FastEdgeTM Series CY2PP3115
Min. -0.3 2.5 - 5% VCC-1.620 Max. 4.6 3.3 + 5% Vcc-1.220 200 VCC-2 VCC+0.3 VCC+0.3 300 -65 -40 40 40 2000 3 50 V-0 +150 +85 60 100 Unit VDC VDC VDC uA VDC VDC VDC mA C C C/W C/W V N.A. Ea. N.A.
Parameter Description VCC Supply Voltage VCC Operating Voltage VBB Output Reference Voltage IBB VTT VIN VOUT LUI TS TA OJc OJa ESDh MSL GATES UL-FLM Output Reference Current Output Termination Voltage Input Voltage Output Voltage Latch-up Immunity Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Flammability Rating
Condition Non-Functional Functional Relative to VCC Relative to VBB Relative to VCC Relative to VCC Relative to VCC Functional Non-functional Functional Functional Functional
-0.3 -0.3
Assembled Die @ 1/8 in.
PECL DC Electrical Specifications
Parameter Description Condition Control (FSEL(A,B,C),CLK_SEL, MR and FSELD) (PECL Single-ended) VCC2.5V 2.5 Operating Voltage 2.5V 5%, VEE = 0.0V VCC3.3V VIL VIH IIN 3.3 Operating Voltage Input Voltage, Low Input Voltage, High Input Current[4] 3.3V 5%, VEE = 0.0V Min. 2.375 3.135 VCC-1.945 VCC-1.165 Max. 2.625 3.465 VCC-1.625 VCC-0.880 I150I Unit V V V V uA
VIL = VILmin. or VIH = VIHmax at VCC = 3.6V 0.1 1.2
Clock input pair CLK0, CLK0#,CLK1,CLK1# (PECL Differential Signals) Differential input voltage[5] Differential operation VPP [6] VCMR Differential cross point voltage Differential operation IIN Input Current[4] VIL = VILmin. or VIH = VIHmax at VCC = 3.6V
1.3 VCC I150I
V V uA
PECL Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#)(PECL Differential Signals) VOH Output High Voltage IOH = -30 mA[7] VCC-1.2 VOL Output Low Voltage VCC = 3.3V 5%, VCC = 2.5V 5% IOL = -5 ma[7] VCC-1.945 VCC -1.945 - VCC-1.620 - -
VCC-0.7 VCC-1.5 VCC-1.3 200 VCC-1.220 2.0 1.0
V V
Supply Current and VBB Maximum Quiescent Supply Current IEE without output termination current[8] [9] VBB Output reference voltage CIN LIN Input pin capacitance Pin Inductance
VEE pin IBB = 200 uA[12]
mA V pF nH
Notes: 4. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. Equivalent to a termination of 50 to VTT. 8. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE orICC = (number of differential output pairs used) x (VOH-VTT)/Rload + (VOL--VTT)/Rload +IEE. 9. VBB is limited to VCC of 3.3V only. See note 17.
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PRELIMINARY
ECL DC Electrical Specifications
Parameter VEE2.5 VEE3.3 VIL VIH IIN VPP VCMR IIN VOH VOL Description -2.5 Negative Power Supply -3.3 Negative Power Supply Input Voltage, Low Input Voltage, High Input Current[10] Differential input voltage[11] Differential cross point voltage Input Current[10] Output High Voltage Output Low Voltage VEE = -3.3V 5%,VEE = -2.5V 5% Maximum Quiescent Supply Current without output termination current[14] Output reference voltage
[12]
FastEdgeTM Series CY2PP3115
Min. -2.375 -33.135 -1.945 -1.165 Max. -2.625 -3.465 -1.625 -0.880 I150I 0.1 VEE+1.2 1.3 -0.5 I150I -1.2 -1.945 -1.945 - -1.620 -0.7 -1.5 -1.3 180 -1.220 Unit V V V V uA V V uA V V
Condition -2.5V 5%, VEE = 0.0V -3.3V 5%, VEE = 0.0V
Control (FSEL(A,B,C),CLK_SEL, MR and FSELD) (ECL single-ended)
VIN = VIL or VIN = VIH Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mA[13] IOL = -5 ma[13]
Clock input pair CLK0, CLK0#,CLK1,CLK1# (ECL differential signals)
ECL Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#)(ECL differential signals)
Supply current and VBB IEE VBB VEE pin IBB = 200 uA mA V
AC Electrical Specifications
Parameter VPP VCMR FCLK TPD Description Differential input voltage[16] Differential cross point Input Frequency[18] voltage[17] Condition Differential operation Differential operation 50% duty cycle Standard load 660 MHz 50% duty cycle Standard load Differential Operation. See Table 2 Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz fo < 1.5 GHz 660 MHz 50% duty cycle Standard load Differential Operation 660 MHz 50% duty cycle Standard load Differential Operation 600 Min. 0.1 VEE + 1.2 Max. 1.3 0 1500 1200 Unit V V MHz ps Clock input pair CLK0, CLK0#,CLK1,CLK1#(PECL or ECL differential signals)
Propagation Delay CLK0 or CLK1 to QA(0:1),QB(0:2),QC(0:3),QD(0:5) pair Differential output voltage (peak-to-peak)
ECL/PECL Clock Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#) (differential) Vo(P-P) 0.45 0.4 0.375 0.3 VCC-1.425 - - 50 60 V
VMCR tsk(O) tsk(O)
Common Voltage Range Output-to-output skew Output-to-output skew (different frequency)
ps ps ps
Notes: 10. Input have internal pullup / pulldown or biasing resistors which affect the input current. 11. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 12. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 13. Equivalent to a termination of 50 to VTT. 14. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH -VTT)/Rload + (VOL -VTT)/Rload +IEE. 15. AC characteristics apply for parallel output termination of 50 to VTT. 16. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 17. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 18. The CY2PP3115 is fully operation up to 1.5 GHz.
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PRELIMINARY
AC Electrical Specifications
Parameter tsk(PP) TJIT(CC) Description Output-to-output skew (part-to-part) Output cycle-to-cycle jitter (deterministic/Intrinsic) All outputs /1 Output cycle-to-cycle jitter (deterministic/Intrinsic) All outputs /2 Condition
FastEdgeTM Series CY2PP3115
Min. - - Max. 200 2 Unit ps ps
50% duty cycle Standard load Differential Operation 500 MHz 50% duty cycle Standard load Differential Operation 660 MHz 50% duty cycle Standard load Differential Operation
-
2
ps
Output cycle-to-cycle jitter (determin660 MHz 50% duty cycle Standard load Differistic/Intrinsic) ential Operation All outputs Bank(A and C)/1, Bank(B and D)/2 660 MHz 50% duty cycle Standard load DifferOutput cycle-to-cycle jitter (determinential Operation istic/Intrinsic) All outputs Bank A/1, Bank(B,C and D)/2 tsk(P) TR,TF TTB Output pulse skew [19] Output Rise / Fall time Total Timing Budget 660 MHz 50% duty cycle Standard load Differential Operation 660 MHz 50% duty cycle Differential 20% to 80% 500 MHz 50% duty cycle Standard load
-
2
ps
-
2
ps
- - -
75 0.3 250
ps ns ps
Table 2. TPD-Propagation Delay 66-MHz 50% Duty Cycle CLK_SEL TPD FSELA FSELB FSELC FSELD 0 1 0 1 0 1 0 1 0 0.900 0.979 0.951 0.962 0.952 1.019 0.986 1.018 1 0.974 0.982 0.974 0.966 0.974 1.021 0.980 1.022 Unit ns ns ns ns ns ns ns ns
Timing Definitions
VCC
VCC = 2.5V or 3.3V VCM R M ax = VCC
VIH
VPP
VPP range 0.1V - 1.3V
VCM R
VIL
VCM R M in = 1.2V
VEE
VEE = 0.0V
Note: 19. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Figure 1. PECL Waveform Definitions
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PRELIMINARY
VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP
FastEdgeTM Series CY2PP3115
V P P r a n g e = 0 .1 to 1 .3 V
VCMR
V IL V C M R m in = V E E - 1 .2 V VEE V E E = - 2 .5 V o r - 3 .3 V
Figure 2. ECL Differential Waveform Definitions
tr, tf, 20-80%
VO(p-p)
Figure 3. ECL/LVPECL Output
VPP / VDIF
TPD VOD
Figure 4. TPD Propagation Delay of Both CLKA or CLKB to Q0-Q9 Pair PECL/ECL to PECL/ECL
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PRELIMINARY
FastEdgeTM Series CY2PP3115
VPP / VDIF
tPLH
tPHL VO(P-P)
tsk(P) Output pulse skew = | tPLH - tPHL |
Figure 5. Output Pulse Skew
VPP / VDIF
Qn VO(P-P)
tsk(0)
Qn+m VO(P-P)
Figure 6. Output-to-output Skew
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PRELIMINARY
Test Configurations
Standard test load using a differential pulse generator and differential measurement instrument.
VTT RT = 50 ohm Pulse Generator Z = 50 ohm
5"
FastEdgeTM Series CY2PP3115
VTT
RT = 50 ohm
Zo = 50 ohm RT = 50 ohm VTT DUT CY2PP3115
Zo = 50 ohm
5"
RT = 50 ohm
VTT
Figure 7. CY2PP3115 AC Test Reference
Applications Information
Termination Examples
C Y2PP3115
V C C = 3 .3 V
5"
1 .3 V RT = 50 ohm
Zo = 50 ohm
5"
RT = 50 ohm 1 .3 V
VEE = 0V
Figure 8. Standard LVPECL - PECL Output Termination
C Y2PP3115
V C C = 0 .0 V
5"
-2 V RT = 50 ohm
Zo = 50 ohm
5"
RT = 50 ohm -2 V
V E E = -3 .3 V
Figure 9. Standard ECL Output Termination
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PRELIMINARY
C Y2PP3115
VCC
5"
FastEdgeTM Series CY2PP3115
VTT RT = 50 ohm
Zo = 50 ohm
5"
VTT R T = 50 ohm VBB
VEE
Figure 10. Driving a PECL/ECL Single-ended Input
C Y2PP3115
V C C = 3 .3 V
5"
3 .3 V 120 ohm
LVDS
Zo = 50 ohm
5"
33 ohm ( 2 p la c e s )
120 ohm 3 .3 V
51 ohm ( 2 p la c e s )
VEE = 0V
L V P E C L to LVDS
Figure 11. Low-voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-voltage Differential
Signaling (LVDS) Interface
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PRELIMINARY
Evaluation Material
FastEdgeTM Series CY2PP3115
Figure 12. Demonstration PCB Part Number
CY2PP3115AI CY2PP3115AIT
Package Type
52-Pin TQFP 52-Pin TQFP - Tape and Reel
Product Flow
Industrial, -40 to 85C Industrial, -40 to 85C
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PRELIMINARY
Package Drawing and Dimensions
FastEdgeTM Series CY2PP3115
52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A52
51-85131-**
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document History Page
Document Title: CY2PP3115 FastEdgeTM Series 1:15 Differential Fanout Buffer Document Number: 38-07502 REV.
** *A
FastEdgeTM Series CY2PP3115
ECN NO.
122042 131090
Issue Date
02/12/03 11/21/03
Orig. of Change
RGL RGL New Data Sheet
Description of Change
Supplied numbers for all specs with TBD after characterization
Document #: 38-07502 Rev.*A
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